The x86 family of processors contains 8 general registers named EAX, EBX, ECX, EDX, ESP, EBP, ESI and EDI. The structure of these eight general registers is shown in FIG. 1.
As seen in FIG. 1, an "E" register designation signifies the entire 32 bits of a register while an "X" register designation signifies the lower 16 bits of a register. With respect to the lower 16 bits of the EAX, EBX, ECX and EDX, the "H" register designation signifies the higher order eight bits from 15 to 8, and the "L" register designation signifies the lower order eight bits from 7 to 0.
The lower 16 bits (bits 0-15) of the general purpose registers may be accessed separately from the upper 16 bits (bits 16-31). In addition, the first four registers in FIG. 1, EAX, EBX, ECX and EDX, are byte writable, i.e. both the first 8 bits (bits 0-7) and the second 8 bits (8-15) of the registers are accessible separately and act as independent registers. For example, if the AH register is written to by an instruction, the AL register remains unchanged.
In the prior art, a separate control line is necessary to write to each byte or word of the eight general purpose registers. For instance, the EAX register requires three control lines: a first to the AL register, a second to the AH register and a third to the EAX register.
In super-pipelined, super-scalar processors such as the one described in U.S. patent application Ser. No. 08/138,281, filed Oct. 18, 1993, entitled, "Pipelined Processor with Register Hardware to Accommodate Multiple Size Registers," which is incorporated by reference herein, the eight general purpose registers are mapped to 32 physical registers contained in a register file. A register translation unit controls the allocation of the 32 physical registers to the eight logical general purpose registers. This allocation is based on various state information described in the above referenced patent application. However, there is no restriction on which logical registers may be addressed to a particular physical register. Any of the 32 physical registers may be mapped to the first four logical register EAX, EBX, ECX, and EDX. Thus, each of the 32 physical registers must be byte writable and, according to prior art techniques, this requires at least three control lines to each of the 32 physical registers. A total of 256 control lines would be necessary for the register file.
A need has thus arisen for a superior way to write to the general purpose register file.
It is thus an object of the present invention to provide an apparatus and method of operating the apparatus for writing to a register file with a reduced number of control lines to each register.
It is a further object of the present invention to provide an apparatus and method of operating the apparatus in which the data in each register may be modified on a byte by byte basis.
It is still a further object of the present invention to provide an apparatus and method of operating the apparatus in which data in subsequent instructions may be quickly forwarded to the processor instruction without first writing the data to the register file.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification.